1. Field of the Invention
This invention generally relates to the field of electronic routing systems, and in particular, to a switch system and method for routing data packets between data ports.
2. Description of the Related Art
A crossbar switch system is a relay operated device or the equivalent that makes a connection between a one-bit signal line in one set of signal lines and a one-bit signal line in another set of signal lines that are essentially orthogonally oriented relative to the signal lines in the one set. In a typical chip, a crossbar switch is used to route data from one data port to another data port. Traditional cell-based, full logic swing crossbar switches involved many switching elements that caused long time delays and high power consumption due to the capacitance of the switching elements and the resistance and capacitance of the metal. Generally, conventional systems routed data by moving the data to be transmitted from a transmitting data port to an input buffer associated with that data port, along a single data line, to an input of a crossbar switch, to an intersection at which a second data line that is also connected to the crossbar switch connects, to an output of the crossbar switch, and to the receiving data port.
In a typical conventional system, a crossbar switch system has six bi-directional data lines, so that there is only one data line for each data port that is numbered for simplicity 1 through 6. Each data port has a data buffer and each data buffer includes block units that each hold a portion of a packet of data. Typically, there are six to eight block units in each data buffer. Each data buffer is coupled to the data line associated with that particular data port. Within the crossbar switch, each data line is coupled to each other data line at an intersection point. Typically, data lines 1, 2, and 3 are positioned horizontally, while data lines 4, 5, and 6 are positioned vertically, so that the lines form a grid or orthogonally oriented data lines. Where two lines intersect and couple together is an intersection point for connecting two data ports.
When the conventional system is operational, a data port loads its associated buffer with the packets of data it seeks to transmit, along with information on the priority of the data in the blocks and on which output port to transmit the data. An arbitration process is also employed to determine the order in which the block units are to transmit over the data line to the crossbar switch. Furthermore, a second arbitration process at the output end determines whether the destination data port is available to receive the data from the data blocks. In conventional systems the arbitration processes occur to provide a priority of transmission. Once a block of data successfully gets access to both the transmitting data line and the receiving data line, the data is transmitted to the crossbar switch and to the destination data port by switching from the transmitting line to the receiving line at the intersection point where the two lines couple together. Similarly, another data port may undertake a similar operation to transmit data from its buffer, along its data lizne to the crossbar switch, to the intersection point where the data line coupled to the destination port couples to the transmitting data line, and out to the destination data port.
The following examples illustrate operation of the conventional systems. As a first example, the data port 1 seeks to transmit its data packets to the data port 6. The data port 1 loads the data packets into the blocks, for example 8 data packets into 8 blocks, of the data port 1 buffer. Each data packet in the data port 1 buffer also includes priority information such as low, medium, or high, as well as address information to direct transmission of the data to the data port 6. The system begins using a first arbitration process to determine the order of transmitting the data packets in the blocks across data line 1 to the crossbar switch. A second arbitration process then determines whether the data port 6 is available to receive the data packets. Once these arbitration processes are completed and a data block is given access to both the data line 1 and the data line 6, the data packet from that data block is transmitted across the data line 1 into the crossbar switch, to the intersection point where the data line 1 couples with the data line 6, onto the data line 6 and out to the data port 6. The problem with this approach is that two arbitration processes decrease system performance as system time and resources are consumed to arrange and order the data packets before transmission begins. Moreover, in the conventional systems, internal blocking is not prevented. Internal blocking is a typical problem in conventional systems where a data packet destined for a particular data port is unable to transmit to that data port because of a transmission of another data packet to that data port.
As a second example, both the data port 1 and the data port 3 seek to transmit their respective data packets to the data port 6. In this implementation, each source data port undergoes a first arbitration process to determine the order to transmit the data packets in the data blocks of their own data buffer across their data line and to the crossbar switch. A second arbitration process is also applied to determine whether the data port 6 is available to receive the data packets, and if so, from where it may receive the data packets, that is either from the data port 1 buffer or the data port 3 buffer. After the two arbitration processes are completed, the data block that won both arbitration processes begins transmitting through its data line, to the crossbar switch, to the data line 6 and onto the data port 6. All other data packets in the data blocks of the data port 1 and the data port 3 must wait to transmit. Once again, the problem with this approach is that the two arbitration processes require significant system time and resources resulting in decreased overall system performance for routing data.
As a third example of a crossbar switch system, the data port 1 seeks to transmit a data packet to the data port 6. In this example, the data port 1 has already undergone the first arbitration process and begins transmission of the data packets from its data input buffer to the data port 6. Subsequently, the data port 3 seeks to transmit its data packets from the data blocks of its data input buffer, with the data packets from some blocks destined for the data port 6 and the data packets from other blocks destined for the data port 5. Moreover, the data blocks holding the data packets to be transmitted to the data port 6 are designated high priority while the data blocks holding the data packets to be transmitted to the data port 5 are designated medium priority.
During the first arbitration process for the data port 3 data packet, the data packets in the data blocks destined for the data port 6 are ordered in terms of their priority for transmission across the data line 3. However, the second arbitration process will not permit transmission to the data port 6 because the data port 6 is unable to receive a data transmission as it is busy receiving data from the data port 1. Moreover, the data in the data blocks destined for the data port 5 are also unable to transmit because it lost the first arbitration process to the high priority blocks that are waiting to transmit across the data line 6 and onto the data port 6. The data packets in the data blocks destined for the data port 6 have been given priority and control of the data line 3, by virtue of prevailing in the first arbitration process, until its transmission is completed. This problem described and associated with the conventional systems is another example of internal blocking. Internal blocking also occurs where multiple data packets having the same priority reside in the same data input buffer. Internal blocking decreases system performance because of the greater time required to transmit the data packets when a higher priority data block is unable to transmit forcing lower priority data blocks to remain idle and wait until the higher priority data block completes its transmission.
Another problem associated with conventional crossbar switch systems involves using a full-swing operational implementation to switch logic states. A drop voltage level necessary to trigger the switch cannot be reached. For example, if the voltage required to switch a state is 2.5 volts ("V") for ON and 0.8 V for OFF and the system voltage level only reaches 2.3 V, a switch may not switch ON. The problem with the prior art systems is that longer clock cycle times are required as the system must wait to switch states until the voltage level can rise back to 2.5 volts. Moreover, the full-swing bus implementation of the prior art systems results in greater power dissipation on the chip. Thus, there is a decrease in the performance and power ratio on the chip.
Therefore, there is a need for a crossbar switch system that provides faster and more efficient data throughput thereby increasing overall switch system performance. There is also a need for a switch data bus that allows for faster and more efficient switching despite being heavily loaded and being wired with resistive interconnect.